1. Field of the Invention
The present invention relates to a pumping circuit which pumps an internal voltage supplied to a semiconductor device, and particularly to an improved pumping circuit for a semiconductor device which is capable of preventing an over pumping by controlling the level of a pumped internal voltage.
2. Description of the Background Art
The pumping circuit is used for pumping the level of an internal voltage when the level of the internal voltage is dropped due to the operation of a semiconductor device.
FIG. 1 illustrates the construction of a related pumping circuit for a semiconductor device.
As shown therein, the related pumping circuit includes a comparator 1 for comparing the level of an internal voltage VCC supplied to an internal circuit with the level of a reference voltage Vref, an oscillator 2 for outputting a clock pulse signal OSC in accordance with an output signal OSCEN from the comparator 1, an inverter INV for receiving the clock pulse signal OSC and outputting a pumping clock signal PEN, and a pumping unit 3 for pumping the level of an external voltage VDD in accordance with the pumping clock signal PEN. The thusly pumped internal voltage VCC is inputted into an inverted terminal (-) of the comparator 1. The comparator 1 receives the internal voltage VCC through the inverted terminal (-) and the reference voltage Vref through the non-inverted terminal (+).
The pumping unit 3 includes a capacitor C connected with an output terminal of the inverter INV, a first switch SW1 connecting a node n1 which is one end of the capacitor C, and a second switch SW2 connecting the node n1 and an internal circuit of the semiconductor device.
The operation of the related pumping circuit for a semiconductor device will now be explained with reference to the accompanying drawing.
The level of the internal voltage VCC supplied to an internal circuit of the semiconductor device is compared with the level of the reference voltage Vref. As a result of the comparison, if the level of the internal voltage VCC is higher than the level of the reference voltage Vref, the output signal OSCEN from the comparator 1 goes low, and if the level of the internal voltage VCC is not higher, the output signal OSCEN goes high.
The inverter INV inverts a clock pulse signal OSC from the oscillator 2 and applies the pumping clock signal PEN to the capacitor C of the pumping unit 3.
If the first switch SW1 of the pumping unit 3 is closed, the voltage level of the node n1 which is the other end of the capacitor C becomes VDD. At this time, if the pumping clock signal PEN goes high, the voltage of the node n1 is increased to twice the external voltage VDD, namely, becomes 2*VDD. At the time when the increase of the voltage is finished, and the second switch SW2 is closed, the pumped voltage (2VDD=VCC) is supplied to the internal voltage of the semiconductor device and is inputted to the inverted terminal (-) of the comparator 1.
When the level of the internal voltage VCC gets below the level of the reference voltage Vref, the pumping unit 3 pumps the level of the voltage synchronously with the clock pulse signal OSC from the oscillator 2, and the pumping operation is continued until the level of the internal voltage VCC exceeds the level of the reference voltage Vref.
If the internal voltage VCC exceeds the reference voltage Vref by the continued pumping operation, the output signal OSCEN from the comparator 1 becomes goes low, and then the pumping operation is stopped.
FIG. 2 illustrates a waveform diagram of output signals from each element of FIG. 1. In FIG. 2, interval A denotes an interval in which the internal voltage VCC is higher than the reference voltage Vref, and interval B denotes an internal in which the pumping operation is continued.
If the internal voltage VCC drops at the point t0, the pumping is started at the time t1. At every pumping operation, the comparison is performed, and the pumping is performed based on the result of the comparison. Here, .DELTA.V1 is the voltage which is increased by the pumping operation, and each interval T1, T2 and T3 denote the time elapsed until the next pumping operation. The pumping clock signal PEN which is an output signal from the inverter INV is high during in the pumping interval.
After the pumping operation is performed four times, the internal voltage VCC exceeds the reference voltage Vref, and then the pumping operation is finished.
In addition, at the time t2 of FIG. 2, the level of the internal voltage VCC is slightly lower than the level of the reference level Vref. However, since the pumping operation is performed once at the time t2, at the time t3 when the pumping operation is finished at time t3, the internal voltage VCC goes above the reference voltage Vref by .DELTA.V. Therefore, the increased voltage .DELTA.V is similar to the voltage .DELTA.V1.
In the related pumping circuit for a semiconductor device, since the reference voltage Vref and the internal voltage VCC are compared for the pumping operation, the internal voltage (VCC=Vref+.DELTA.V), when the pumping operation is finished, is higher than the reference voltage Vref by .DELTA.V. The voltage .DELTA.V is proper as it is closer to 0; however, the voltage .DELTA.V may be almost as large as the voltage .DELTA.V1. Therefore, an unstable voltage may be supplied to the internal circuit of the semiconductor device due to this over pumping, so that the operation of the internal circuit becomes unstable.
In order to overcome the above-described problem, a pumping circuit having a small pumping capability and a pumping circuit having a large pumping circuit are used, in which a circuit capable of forming additional discharging path is provided for thereby decreasing the level of the internal voltage VCC.
However, construction of such circuit is complicated.